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LH168P
LH168P
DESCRIPTION
The LH168P is a 309-output TFT-LCD source driver IC which can simultaneously display 262 144 colors in 64 gray scales.
309-output TFT-LCD Source Driver IC
PIN CONNECTIONS
350-PIN TCP TOP VIEW
FEATURES
* Selectable number of LCD drive outputs : 309/300 * Built-in 6-bit digital input DAC * Possible to display 262 144 colors in 64 gray scales with reference voltage input of 11 gray scales : This reference voltage input corresponds to correction and intermediate reference voltage input can be abbreviated * Cascade connection * Sampling sequence : Output shift direction can be selected XO1, YO1, ZO1/XO103, YO103, ZO103 or ZO103, YO103, XO103/ZO1, YO1, XO1 * Shift clock frequency : 55 MHz (MAX.) * Supply voltages - VCC (for logic system) : +3.0 to +5.5 V - VLS (for LCD drive system) : +3.0 to +5.5 V * Package : 350-pin TCP (Tape Carrier Package)
XO1 1 YO1 2 ZO1 3
350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310
GND VLS V9 V7 V5 V3 V1 XI5 XI4 XI3 XI2 XI1 XI0 YI5 YI4 YI3 YI2 YI1 YI0 SPOI GND MODE CK VCC SPIO LS ZI5 ZI4 ZI3 ZI2 ZI1 ZI0 LBR V0 V2 V4 V6 V8 V10 VLS GND
XO103 307 YO103 308 ZO103 309
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
CHIP SURFACE
LH168P
PIN DESCRIPTION
PIN NO. 1 to 309 310, 330, 350 311, 349 312 to 317 318 319 to 324 325 326 327 328 329 331 332 to 337 338 to 343 344 to 348 SYMBOL XO1-ZO103 GND VLS V10, V8, V6, V4, V2, V0 LBR ZI0-ZI5 LS SPIO VCC CK MODE SPOI YI0-YI5 XI0-XI5 V1, V3, V5, V7, V9 I/O O - - I I I I I/O - I I I/O I I I DESCRIPTION LCD drive output pins Ground pins Power supply pins for analog circuit Reference voltage input pins Shift direction selection input pin Data input pins Latch input pin Start pulse input/cascade output pin Power supply pin for digital circuit Shift clock input pin 309/300-output selection input pin Start pulse input/cascade output pin Data input pins Data input pins Reference voltage input pins
2
LH168P
BLOCK DIAGRAM
VCC GND 327 330 GND GND 310 350
MODE 329 LBR 318 SPOI 331 CK 328 12 XI0 338 XI5 343 YI0 332 YI5 337 ZI0 319 6 ZI5 324 6 LS 325 V0 317 V1 344 LEVEL SHIFTER V2 316 V3 345 V4 315 V5 346 V6 314 V7 347 V8 313 V9 348 V10 312 1 2 3 307 308 309 XO103 YO103 ZO103 OUTPUT CIRCUIT REFERENCE VOLTAGE GENERATION CIRCUIT 6 6 6 311 VLS 349 VLS 6 6 6 HOLD MEMORY 6 6 DATA LATCH 6 6 103 SHIFT REGISTER 326 SPIO
SAMPLING MEMORY
64
DA CONVERTER
XO1 YO1 ZO1
3
LH168P
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Shift Register Data Latch Sampling Memory Hold Memory Level Shifter Reference Voltage Generation Circuit DA Converter Output Circuit FUNCTION Used as a bi-directional shift register which performs the shifting operation by CK and selects bits for data sampling. Used to temporary latch the input data which is sent to the sampling memory. Used to sample the data to be entered by time sharing. Used for latch processing of data in the sampling memory by LS input. Used to shift the data in the hold memory to the power supply level of the analog circuit unit and sends the shifted data to DA converter. Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit. Used to generate an analog signal according to the display data and sends the signal to the output circuit. Used as a voltage follower, configured with an operational amplifier and an output buffer, which outputs analog signals of 64 gray scales to LCD drive output pin.
INPUT/OUTPUT CIRCUITS
VCC
I
To Internal Circuit
GND
Applicable pins CK, LS, LBR, XI0-XI5, YI0-YI5, ZI0-ZI5
Fig. 1 Input Circuit (1)
VCC
VCC
I
To Internal Circuit
GND
Applicable pin MODE
Fig. 2 Input Circuit (2)
4
LH168P
Pch Tr
VCC
I
O
Output Signal
Output Control Signal Nch Tr GND
VCC
To Internal Circuit
GND
Applicable pins SPIO, SPOI
Fig. 3 Input/Output Circuit
VLS
Operational Amplifier O
+ -
From Internal Circuit
GND
Applicable pins XO1-XO103, YO1-YO103, ZO1-ZO103
Fig. 4 Output Circuit
5
LH168P
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VCC VLS GND SPIO SPOI FUNCTION Used as power supply pin for digital circuit, connected to +3.0 to +5.5 V. Used as power supply pin for analog circuit, connected to +3.0 to +5.5 V. Used as ground pin, connected to 0 V. Used as input pins of start pulse and also used as output pins for cascade connection. When "H" is input into start pulse input pin, data sampling is started. On completion of sampling, "H" pulse is output to output pin for cascade connection. Pin functions are selected by LBR. For selecting, refer to "Functional Operations". Used as input pin for selecting the shift register direction. For selecting, refer to "Functional Operations". Used as input pin for parallel transfer from sampling memory to hold memory. Data is transferred at the rising edge and output from LCD drive output pin. Used as shift clock input pin. Data is latched into sampling memory from data input pin at the rising edge. Used as reference voltage input pins. Hold the reference voltage fixed during the period of LCD drive output. For relation between input data and output voltage values, refer to "Output Voltage Value". For internal gamma correction, refer to "Gamma Correction Value". Used as data input pins of R, G, and B colors. 6-bit data are input from data pins at the rising edge of CK. For relation between input data and output voltage values, refer to "Output Voltage Value". Select the data to be entered into X, Y, and Z according to picture element arrays of the panel. Used as input pin for selecting the number of LCD drive outputs (309 outputs or 300 outputs). When "L" is entered, it is 309-output mode. When "H" is entered, it is 300-output mode. This pin is pulled up at the inside. Used as LCD drive output pins which output the voltage corresponding to the data input pins (XI0 to XI5, YI0 to YI5, ZI0 to ZI5). When 300-output mode, 9 output pins (XO51 to XO53, YO51 to YO53, ZO51 to ZO53) are invalid. Invalid output pins must be opened. Data of XO1 to XO103 correspond to XI0 to XI5. Data of YO1 to YO103 correspond to YI0 to YI5, and data of ZO1 to ZO103 correspond to ZI0 to ZI5. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value".
LBR LS CK
V0-V10
XI0-XI5 YI0-YI5 XI0-ZI5
MODE
XO1-XO103 YO1-YO103 ZO1-ZO103
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LH168P
Functional Operations
The following describes the relation between LBR pin, SPOI pin, SPIO pin and output direction.
OUTPUT DIRECTION RIGHT SHIFT (XO1, YO1, ZO1/XO103, YO103, ZO103) H Input Output LEFT SHIFT (ZO103, YO103, XO103/ZO1, YO1, XO1) L Output Input
PIN LBR SPOI SPIO
NOTE :
Color data corresponding to X, Y, and Z vary depending on the output direction.
7
LH168P
Output Voltage Value
Two voltages are selected from all of the reference voltages (V0-V10) by the upper 3-bit data (D5, D4 and D3) of the 6-bit input data (D5, D4, D3, D2, D1 and D0) taken by time sharing, and intermediate
INPUT DATA 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F INPUT DATA 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
value is determined by the lower 3-bit data (D2, D1 and D0). Relation between input data and output voltage values is shown below.
OUTPUT VOLTAGE V0 V1 V2 + (V1 - V2) x 6/7 V2 + (V1 - V2) x 5/7 V2 + (V1 - V2) x 4/7 V2 + (V1 - V2) x 3/7 V2 + (V1 - V2) x 2/7 V2 + (V1 - V2) x 1/7 V2 V3 + (V2 - V3) x 7/8 V3 + (V2 - V3) x 6/8 V3 + (V2 - V3) x 5/8 V3 + (V2 - V3) x 4/8 V3 + (V2 - V3) x 3/8 V3 + (V2 - V3) x 2/8 V3 + (V2 - V3) x 1/8 V3 V4 + (V3 - V4) x 7/8 V4 + (V3 - V4) x 6/8 V4 + (V3 - V4) x 5/8 V4 + (V3 - V4) x 4/8 V4 + (V3 - V4) x 3/8 V4 + (V3 - V4) x 2/8 V4 + (V3 - V4) x 1/8 V4 V5 + (V4 - V5) x 7/8 V5 + (V4 - V5) x 6/8 V5 + (V4 - V5) x 5/8 V5 + (V4 - V5) x 4/8 V5 + (V4 - V5) x 3/8 V5 + (V4 - V5) x 2/8 V5 + (V4 - V5) x 1/8 V5
OUTPUT VOLTAGE V6 + (V5 - V6) x 7/8 V6 + (V5 - V6) x 6/8 V6 + (V5 - V6) x 5/8 V6 + (V5 - V6) x 4/8 V6 + (V5 - V6) x 3/8 V6 + (V5 - V6) x 2/8 V6 + (V5 - V6) x 1/8 V6 V7 + (V6 - V7) x 7/8 V7 + (V6 - V7) x 6/8 V7 + (V6 - V7) x 5/8 V7 + (V6 - V7) x 4/8 V7 + (V6 - V7) x 3/8 V7 + (V6 - V7) x 2/8 V7 + (V6 - V7) x 1/8 V7 V8 + (V7 - V8) x 7/8 V8 + (V7 - V8) x 6/8 V8 + (V7 - V8) x 5/8 V8 + (V7 - V8) x 4/8 V8 + (V7 - V8) x 3/8 V8 + (V7 - V8) x 2/8 V8 + (V7 - V8) x 1/8 V8 V9 + (V8 - V9) x 6/7 V9 + (V8 - V9) x 5/7 V9 + (V8 - V9) x 4/7 V9 + (V8 - V9) x 3/7 V9 + (V8 - V9) x 2/7 V9 + (V8 - V9) x 1/7 V9 V10
8
LH168P
(gamma) Correction Value
Between reference voltage input pins, 7 or 8 resistors of the same resistance value are connected in series. When the resistance ratio between respective reference voltage input pins matches the reference voltages (V1 to V9) for correction of LCD panel, the external power supply of the intermediate voltages (for V1 to V9 pins) is not required.
LH168P V0 V1 V2 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 7 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 7 equal parts
External Reference Voltage
V3 V4 V5 V6 V7 V8 V9 V10
The following shows the ratio of correction resistance, when R0 equals 1.
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 1.05 1.42 0.84 0.66 0.84 0.90 1.50 2.77 2.00 1.00
9
LH168P
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. VCC / logic input / VLS, V0-V10 When disconnecting the power supply, follow the reverse sequence. Reference voltage input The relation of the reference voltage input is shown here. GND < V0 V1 V9 V10 < VLS or VLS > V0 V1 V9 V10 > GND Maximum ratings When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings. Target output load This IC is designed for a 150 pF output load capacity. When using this IC for other than 150 pF panels, confirm the device is having no problem before using it.
RATING -0.3 to +6.0 -0.3 to +6.0 -0.3 to VLS + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VLS + 0.3 -45 to +125 UNIT V V V V V V C 1, 2 NOTE
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage SYMBOL VCC VLS VI Input voltage VI VO VO TSTG APPLICABLE PINS VCC VLS V0-V10 SPIO, SPOI, CK, LS, MODE, LBR, XI0-XI5, YI0-YI5, ZI0-ZI5 SPIO, SPOI XO1-ZO80
Output voltage Storage temperature
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to GND (0 V).
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage Reference voltage input Clock frequency LCD drive output load capacity Operating temperature SYMBOL VCC VLS V0-V10 fCK CL TOPR -20 MIN. +3.0 +3.0 0 TYP. MAX. +5.5 +5.5 VLS 55 150 +75 UNIT V V V MHz pF C NOTE 1
NOTE :
1. The applicable voltage on any pin with respect to GND (0 V).
10
LH168P
ELECTRICAL CHARACTERISTICS DC Characteristics
(VCC = VLS = +3.0 to +5.5 V, TOPR = -20 to +75 C)
MIN. TYP. MAX. UNIT GND 0.3VCC V 0.7VCC VCC V GND GND + 0.4 V VCC - 0.4 VCC V 10 400 10 A A A NOTE
PARAMETER SYMBOL CONDITIONS APPLICABLE PINS XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, Input "Low" voltage VIL VIH SPOI, CK, LS, LBR, MODE Input "High" voltage Output "Low" voltage VOL IOL = 0.3 mA SPIO, SPOI Output "High" voltage VOH IOH = -0.3 mA XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, IILL1 SPOI, CK, LS, LBR Input "Low" current IILL2 MODE XI0-XI5, YI0-YI5, ZI0-ZI5, SPIO, Input "High" current VILH SPOI, CK, LS, LBR, MODE fCK = 55 MHz Supply current ICC1 fLS = 50 kHz (In operation mode) (Data sampling state) fCK = 55 MHz VCC-GND Supply current fLS = 50 kHz ICC2 (In standby mode) SPI = GND is fixed. (Standby state) fCK = 55 MHz Supply current ILS1 fLS = 50 kHz (In operation mode) (Data sampling state) fCK = 55 MHz VLS-GND fLS = 50 kHz Supply current ILS2 SPI = GND is fixed. (In standby mode) (Standby state) Output voltage range VOUT Deviations between XO1-ZO103 VOD output voltage pins Output current IO1, IO2 Resistance between RGMA V0-V10 reference voltage input pins
12
mA
4
mA
8
mA
7
mA
GND + 0.1 -20 20 10 50 20
VLS - 0.1 20
V mV A 1 2
30
k$
NOTES :
1. Criterion of evaluating voltage deviations. (a) Between output voltage pins Measuring values : Output voltage value at the time after 10 s at the rising edge of LS. (Average of several times) (Conditions) Output load capacity is 150 pF. In a state when the reference voltage is fixed. Expecting values : Calculated following these specifications. (Conditions) In a state when the reference voltage is fixed. (b) Between LCD drivers Measuring values : Applicable to (a). (Conditions) Applicable to (a). Expecting values : Applicable to (a). (Conditions) Applicable to (a). Each input voltage between the LCD drivers must be made perfectly equal by connecting corresponding reference voltage input pins. 2. IO1 : Applied voltage = 3.0 V for output pins XO1 to ZO103. Output voltage = 2.5 V for output pins XO1 to ZO103. VCC = VLS = 5.0 V IO2 : Applied voltage = 2.0 V for output pins XO1 to ZO103. Output voltage = 2.5 V for output pins XO1 to ZO103. VCC = VLS = 5.0 V
11
LH168P
AC Characteristics
PARAMETER Clock frequency "H" level pulse width "L" level pulse width Input rise time Input fall time Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse width Start pulse output delay time LCD drive output delay time LS signal-SPI signal setup time LS signal-CK signal hold time LS signal "H" level width SYMBOL CONDITIONS fCK tCWH tCWL tCR tCF tSUD tHD tSUSP tHSP tWSP tDSP tDO tLSSP tHLS tWLS CL = 15 pF CL = 150 pF
(VCC = VLS = +3.0 to +5.5 V, TOPR = -20 to +75 C)
APPLICABLE PINS MIN. 4 4 10 10 XI0-XI5, YI0-YI5, ZI0-ZI5 4 0 4 0 SPIO, SPOI 1 -------fCK 12 XO1-ZO103 1 -------fCK LS 7 1 -------fCK 10 TYP. MAX. 55 UNIT MHz ns ns ns ns ns ns ns ns ns ns s ns ns ns
CK
12
LH168P
Timing Chart
1 fCK CK tSUSP SPIO Input (SPOI) tWSP tSUD tHD tHSP tCR tCWH tCWL
1 tCF
2
XI0-XI5 YI0-YI5 ZI0-ZI5
1
2
CK
LAST - 1 tDSP
LAST
SPIO Output (SPOI) tHLS LS tLSSP SPIO Input (SPOI) tDO tSUSP tHSP tWLS
XO1-ZO103
Target voltage (6-bit accuracy)
13
PACKAGES FOR LCD DRIVERS
PACKAGES
0.75MAX. Backside 1.0MAX. Total
(Unit : mm)
[0.3]
[0.75] 0.15MAX. Pattern side (0.07) 0.5 0.2 2-O0.6 (PI hole) 2-R0.5 (Cu)
0.2 0.3
Sprocket center
2-O0.8 (Cu hole)
2-O1.2 (PI hole)
2-R0.7 (SR)
2-O1.8 (Cu)
Flexible slit
Chip center
(0.035) 4.750.05 1.420.05
1.420.05
4.3MAX.(Resin area)
0.8 (SL)
0.8 (SL)
O1.0 (Good device hole)
1.00.05 2.5 (SL) 2.0 (SL) 4.5 (SL) 2.1 (Backside PI coat) 4.3 (Backside PI coat) 2.4 (SL) 4.9 (Backside PI coat) 4.6 (SL) 7.2
0.05
1.6 (Backside PI coat) 1.0 (SL) [3.0TYP. (2.85MIN.)] 0.5 (SL)
1.6 (Backside PI coat) 1.0 (SL) 1.6 (Backside PI coat) 1.0 (SL) [1.65TYP. (1.50MIN.)] 0.24
0.02
[0.40]
20 0. [C
(Hole)
5.2 (SL) 6.40.15(SR) (On the output leads) 0.05 (Mark) 7.4 [8.05 (E.L.)]
LH168PF
0.8 (SL)
8.40.15(SR) (On the output leads) 10.4 (SL) [11.4 (E.L.)] [19.45 (E.L.)] 11.7 12.45 (SL) 12.70.5(Good device hole)
[0.65] [1.65TYP. (1.50MIN.)]
UPILEX is a trademark of UBE INDUSTRIES, LTD..
14
0.240.02
]
Tape width Tape type Perforation pitch
ZO1 YO1 XO1 VCOM3 VCOM3 VCOM3 VCOM2 VCOM2 VCOM2 VCOM2 VCOM2 VCOM1 VCOM1
o Tape Specification
DUMMY VCOM6 VCOM5 VCOM4 DUMMY GND VLS V10 V8 V6 V4 V2 V0 LBR ZI0 ZI1 ZI2 ZI3 ZI4 ZI5 LS SPIO VCC CK MODE GND SPOI YI0 YI1 YI2 YI3 YI4 YI5 XI0 XI1 XI2 XI3 XI4 XI5 DUMMY V1 V3 V5 V7 V9 VLS GND DUMMY VCOM3 VCOM2 VCOM1 DUMMY
12.6 (SL) 12.3 (SR) 24.2 (SL) 0.05 (Holes) 23.6 P0.46 x (52 - 1) x 0.99869 = 23.4290.03 W0.230.02 0.5 (Good device hole) 11.5 5.0 (SL) 7.0 (SL) 5.0 (SL) 5.0 (SL) 8.0 (SL)
Flexible slit
MAX. (Resin area) 20.4 0.015 W0.040.015 P0.070 x (332 - 1) x 0.99866 = 23.139 11.95 (SR) 11.95 (SR) 24.00.04(Mark) 24.4 (SL) 25.0 (Backside PI coat) [26.0 (E.L.)]
P0.065 x (358 - 1) = 23.205 W0.033
12.6 (SL) 12.3 (SR)
XO1
35 mm Super wide 5 pitches
ZO54 YO54 XO54 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY ZO50 YO50 XO50
Device center
P0.46 x (52 - 1) = 23.46 W0.23 24.4 (SL) 0.05 21.4
Film center
25.0 (Backside PI coat)
34.975 31.82 [26.0 (E.L.)]
Substrate Adhesive Cu foil [thickness] Solder resist
VCOM6 VCOM6 VCOM5 VCOM5 VCOM5 VCOM5 VCOM5 VCOM4 VCOM4 VCOM4 ZO103 YO103 XO103
o Tape Material
ZO103
UPILEX S75 #7100 FQ-VLP 15 m Polyimide SSF
Flexible slit
PACKAGES FOR LCD DRIVERS
0.75MAX. Backside
1.0MAX. Total
2-R0.5 (Cu)
[0.3]
[0.75] 0.15 Pattern side 0.5 0.2 2-R0.9 (Cu)
2-O0.6 (PI hole)
(0.1)
MAX.
Sprocket center
2-O0.8 (Cu hole)
2-R0.6 (SR)
2-O1.2 (PI)
Chip center
Flexible slit
(0.05)
0.2 0.3
4.3MAX. (Resin area) 2-R0.5 2-R0.5
1.420.05
4.750.05 1.420.05
1.4 (SL)
2.1 (Backside PI coating) 1.6 (Backside PI coating) O1.0 (Good device hole) 1.0 (SL) 4.6 (SL) 6.0 (SL) 2.4 (SL) 4.5 (SL) 10.5 (SL) 4.9 (Backside PI coating) 5.2 (SL)
0.15 (SR) 6.4 (On the output leads) 7.40.05(Mark) [8.05 (E.L.)]
1.6 (Backside PI coating) 4.3 (Backside PI coating) 1.0 (SL) [0.40] 1.6 (Backside PI coating) 1.0 (SL) [1.65TYP. (1.50MIN.)] 0.240.02 [0.65] [1.65TYP. (1.50MIN.)]
7.2 [3.2TYP. (3.05MIN.)] 0.5 (SL)
0.05
(Hole)
LH168PF1
0.8 (SL)
8.20.15(SR) (On the output leads) 10.4 (SL) [11.4 (E.L.)] [19.45 (E.L.)] 11.7 12.45 (SL) 12.70.5(Good device hole)
15
0.24
[C 0. 20 ]
2.50.05
0.02
Tape width Tape type Perforation pitch
ZO1 YO1 XO1 VCOM3 VCOM3 VCOM3 VCOM2 VCOM2 VCOM2 VCOM2 VCOM2 VCOM1 VCOM1
o Tape Specification
DUMMY VCOM6 VCOM5 VCOM4 GND VLS V10 V8 V6 V4 V2 V0 LBR ZI0 ZI1 ZI2 ZI3 ZI4 ZI5 LS SPIO VCC CK MODE GND DUMMY SPOI YI0 YI1 YI2 YI3 YI4 YI5 XI0 XI1 XI2 XI3 XI4 XI5 POL V1 V3 V5 V7 V9 VLS GND DUMMY VCOM3 VCOM2 VCOM1 DUMMY
12.3 (SR) 12.0 (SL) 24.2 (SL) 23.60.05(Holes) P0.46 x (52 - 1) x 0.99869 = 23.4290.025 W0.230.02 11.50.5(Good device hole) 5.0 (SL) 5.0 (SL) 5.0 (SL) 7.0 (SL) 8.0 (SL)
P0.070 x (332 - 1) x 0.99866 = 23.1390.015 W0.040.015 23.6 (Backside PI coating) 11.95 (SR) 11.95 (SR) 0.02 (Mark) 23.968 24.8 (SL) 25.4 (Backside PI coating) [26.0 (E.L.)]
12.3 (SR) 12.0 (SL)
35 mm Super wide 5 pitches
ZO54 YO54 XO54 ZO53 YO53 XO53 ZO52 YO52 DUMMY DUMMY DUMMY XO52 ZO51 YO51 XO51 ZO50 YO50 XO50
Device center
23.6 (Backside PI coating)
23.0 (SL) 20.00.05 20.4MAX. (Resin area)
34.975 31.82 [26.0 (E.L.)]
Film center
23.0 (SL)
Substrate Adhesive Cu foil [thickness] Solder resist
Flexible slit
VCOM6 VCOM6 VCOM5 VCOM5 VCOM5 VCOM5 VCOM5 VCOM4 VCOM4 VCOM4 ZO103 YO103 XO103
o Tape Material
UPILEX S75 #7100 FQ-VLP 15 m Polyimide SSF
1.4 (SL)
Flexible slit

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